High Resolution Clock Generators for Globally-Asynchronous Locally-Synchronous Designs

As explained in the companion paper by Thomas Villiger et. al. and in [1] a GALS system is partitioned into many Locally-Synchronous Islands, such as the one shown in Fig. 1. The GALS approach restricts the asynchronous parts to some well-known circuits contained in a Self-Timed Wrapper around each Synchronous Island and makes it possible to use the synchronous design paradigm for the Synchronous Islands. The Self-timed Wrapper contains asynchronous port controllers, an extension for adding testability, and a Local Clock Generator for the Synchronous Island. The self-timed approach does away with the need to time-align the operation of all modules within the framework of a common base clock period. Instead, each module is driven from a Local Pausable Clock Generator which is controlled (paused) by asynchronous port controllers such as to prevent any timing violations from occurring within the Synchronous Island’s data interface. Local Clock Generator Self-Timed Wrapper Locally-Synchronous Island Port Controller Port Port Test Extension Port Controller Figure 1: GALS Module consisting of a LocallySynchronous Island (LSI) and a Self-timed Wrapper The viability of our GALS approach has recently been demonstrated by the implementation of a SAFER-SK128 crypto-system on silicon. The respective results were presented at the ACiD-workshop in 2001. Experimental results showed that the quality of the Local Clock Generator greatly impacts the GALS system’s performance. A Local Clock Generator therefore ideally meets all of the following requirements: • Tunable over a large frequency range up to 1 GHz. • The oscillator has to be pausable and must recover operation (e.g. restart the oscillation process) without anomalies. • To facilitate process migration, it should be possible to reassemble the oscillator without long simulation runs and without complicated estimation of process parameters. The oscillator therefore ideally consists of standard cells routinely available in any cell library. • The frequency of the oscillator has to be tunable with a high resolution, e.g. the aim is to minimize the increase or decrease of the clock period per tuning step. • One of the big advantages of GALS is the reduction of power consumption by getting rid of the global clock tree (which can absorb up to 30% of the chip’s total power). The smaller local oscillator shall therefore not consume too much power. Improved Local Clock Generator: A linear time resolution leads to a nonlinear frequency resolution and therefore to large gaps in the tunability of the frequencies as shown in Fig. 3. The Local Clock Generator used so far is shown in Fig. 2 and uses delay slices of type dslC in Fig. 5, which yield only a coarse resolution at frequencies above 300 MHz. Therefore, new local clock generator architectures with increased tuning range and frequency resolution are being developed for use within the GALS system. Examples of tunable delay elements with sub-gate resolution are shown in Figures 6, 4 and 7. The inverter matrix in Fig. 7 proposed by Hsu [2] seems to be most promising, as it allows the generation of sub-gate resolution using available standard cells exclusively. Also, the resolution only depends on the number of delay banks and inverters being used. With the addition of these new local clock generators, it will be possible to obtain better performance from individual GALS modules. The presentation will focus on a comparative overview of available alternatives to achieve sub-gate resolution at high oscillation frequencies. Further, the Local Clock Generator used so far is explained and its drawbacks and possible improvements will be discussed. It is planned to evaluate these alternative clock concepts in terms of area, power, design effort, frequency resolution and portability. References [1] Muttersbach, Jens ”Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems”, Diss. ETH Zurich No. 14155, 2001 [2] Hsu, Terng-Yin; Wang, Chung-Chung; Lee, Chen-Yi ”Design and Analysis of a Portable High-Speed Clock Generator”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47 no. 8, 2000